flow: Use Virtual Clocks for IO Delays#4294
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maliberty merged 10 commits intoJun 17, 2026
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This pull request updates the SDC constraints across multiple designs to define virtual clocks and set matching clock latencies for both real and virtual clocks, alongside updating the OpenROAD submodule. The review feedback highlights several critical issues in the constraints: an undefined variable $clk_core_name in the I2C GPIO expander design, a missing virtual clock definition for vclk_i in the Mempool Group design, and missing clock latency configurations for the JTAG clocks in the Microwatt design.
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Create virtual IO reference clocks for SDC input and output delay constraints so post-CTS propagated real clocks do not become the external timing reference. Propagate only the real design clocks in post-CTS SDCs while preserving virtual clock latency for IO timing. Update the OpenROAD submodule pointer to include the CTS virtual clock latency fix used by these constraints. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Rebase metric thresholds for designs affected by the updated OpenROAD build used in CI.\n\nAdjust timing and antenna limits to match the observed public and secure CI outputs while preserving existing metric coverage.\n\nExclude the local OpenROAD submodule checkout change from this commit. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
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Set real and virtual IO clock latency estimates from propagated CTS clock latency reported in CI artifacts. Use the representative average of source and target clock latency from 4_cts_final reports so IO virtual clocks track observed post-CTS insertion delay more closely. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Relax metric thresholds for designs affected by the updated IO clock latency estimates. Use the latest public and secure CI results to update timing and wirelength rules for failing designs. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Update the OpenROAD submodule to the private secure-fix-cts-propagated-clock commit that preserves virtual clock latency during CTS. This lets the SDC virtual IO clock latency changes affect post-CTS timing and downstream QoR in CI. Only the OpenROAD submodule pointer is changed. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
…agated-clock # Conflicts: # tools/OpenROAD Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Update metadata golden files for the public PR-4294 merge run. Use the PR-4294-merge The-OpenROAD-Project#10 report metrics for designs that failed the public inline metric comparison so the expected metric baseline matches the virtual IO clock constraints. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Revert the deprecated metadata-base-ok.json updates from the previous metric rebase. Update rules-base.json for the public PR-4294 merge run using the reported metrics so the public metric checks match the virtual IO clock constraints. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Update the gf12 ariane rules baseline from secure CI build 16. Relax the CTS setup TNS rule to match the virtual IO clock timing result while keeping deprecated metadata-base-ok.json files untouched. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Add an empty commit to retrigger the public PR merge CI after the rules rebase. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
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maliberty
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Jun 17, 2026
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